Verification Methodologies Made Easy — Aldec

Most FPGA designers don't know much about formal methodologies for verification. It's too bad, because today's complicated FPGA designs can really take advantage of standardized methodologies like UVM. In this episode of Chalk TalkHD Amelia and Jerry Kaczynski (Aldec) are going to unscramble the anagrams and get you on your way to understanding and harnessing the power of universal verification methodologies - so you can start applying them to your next design.