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My chip testing The chip C2S0042 Successfully Tested Using Digilent Analog Discovery Studio.

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Physical Verification LVS PEX Post-layout Simulation using Verilog netlist

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Part 1 Common Source Amplifier Design using SCL 180nm

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IINVENTIVE 2026

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NIT Silchar VLSI Lab Tour

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Bharat Innovates 2026NIT Silchar Project Proposal

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A brief session on Analog IC design ISchematic to Chip Tapeout at Siliguri Institute of Technology

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Neural Amplifier Design as a part of MeitY Funded SMDP C2SD Project R&D Fair IInventive 2025

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Part 3 Layout of Differential Amplifier using gpdk90nm Post Layout Simulation

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Part 1 How to Design Differential amplifier using GPDK90nm Technology

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Part 2 How to Design Practical Differential Amplifier using gpdk90nm Technology

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How to find process parameter of any technology node UMC180 Cadence

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Two Stage Op-amp design AC Analysis DC Analysis PSRR CMRR ICMR Noise using TSMC65nm

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How To Find Channel Length Modulation Coefficient Lambda using MOS Output Characteristics

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Tutorial 2 Universal Logic Gates Design and simulation using LTSpice NAND Gate NOR Gate

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Tutorial 1 CMOS inverter Design & Simulation using LTspice VTC Transient Analysis

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Part 4 Two-Stage Op-amp Layout verification and Post-Layout simulation DRC LVS PEX ASSURA

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Part 3. Layout of Two stage Opamp UMC180nm Technology

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Part 2 Simulation and analysis of 2-stage op-amp PSRR SLEW RATE ICMR POWER

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Part 1 Analog Circuit Sizing using Softcomputing Algorithm AC Analysis Gain Phase CMRR

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Current Mirror Layout using TSMC65nm Technology with interdigitation matching.

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Verilog Coding and Simulation in Cadence Virtuoso Analog Environment AMS Simulation

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Differential Pair Layout using Common Centroid Matching Technique in TSMC 65nm PDK

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PART 2 Logical Equivalence Check (LEC) using Cadence Conformal Tool

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Standard Cell Layout Using Euler Path Optimisation demonstrated in Cadence Virtuoso.

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PART 1 RTL SYNTHESIS USING CADENCE GENUS TOOL

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Tools required for digital IC Design flow

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Part 2 FPGA IN LOOP VIO ILA SLICE IP CORE BLOCK IMPLEMENTATION

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Part 1 NEXYS 4 DDR FPGA IMPLEMENTATION

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Analog Mixed Signal IC Design LEF File Generation using Cadence Abstract Tool Tutorial

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