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For many years I was in the Department of Computer Science at Portland State University. I have an Sc.B. from Brown University and a Ph.D. from the Oregon Gr...

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Clever C Malloc Code Walk-Thru

Arduino Nano Every Schematic Explained

RISC-V 21-Virtual Memory #6 TLB Flush, sfence.vma

RISC-V 20-Virtual Memory #5 Sv39, Sv48, Sv57

RISC-V 19-Virtual Memory #4 ASID, TLB Design

RISC-V 18-Virtual Memory #3 Demand Paging

RISC-V 17-Virtual Memory #2 MMU, Tree Walks, Page Faults, Megapages

RISC-V 16-Virtual Memory #1 Page Tables, PTEs, Sv32

RISC-V Privilege #14 Misc CSRs (Control and Status Registers)

RISC-V Privilege #15 PMP-The Physical Memory Protection System

RISC-V Privilege #13 mstatus, sstatus - details

RISC-V Privilege #12 Exceptions, Interrupts, and the PLIC

RISC-V Privilege #11 Intro to Trap Processing and Exceptions

Avoiding The AI Apocalypse

RISC-V Assembly Code #8 Floating Point-IEEE 754

RISC-V Assembly Code #9 Floating Point Instructions (pt. 1)

RISC-V Assembly Code #10 Floating Point Instructions (pt. 2)

RISC-V Assembly Code #7 Example Program

RISC-V Assembly Code #6 Multiply, Divide Instructions

RISC-V Assembly Code #5 RV32 v RV64

RISC-V Assembly Code #2 ALU, Load, Store Instructions

RISC-V Assembly Code #1 Course Intro, Registers

RISC-V Assembly Code #4 Asm Directives, Pseudo Instructions

RISC-V Assembly Code #3 Branch, Jump, Call, Return, etc

RISC-V Verilog Implementation (FemtoRV)

RISC-V Architecture Instruction Encoding

EveCore 2525 Design Decisions, Lessons, Mistakes

EveCore 2425 Project Ideas + Future Work

EveCore 2225 ISA - Long Version

EveCore 2325 ALU Module - More Detail