Latest Videos
[VLSI FIFO ] full and empty logic for FIFO verilog code for FIFO FIFO logic
VLSI-LEARNINGS
10.0K views·5 years ago
Sequence detector 101001 overlapping mealy FSM Sequence detector
VLSI-LEARNINGS
1.8K views·5 years ago
Design decoder using mux decoder implementation using multiplexer
VLSI-LEARNINGS
22.7K views·5 years ago
Full adder using 2x1 mux full adder using 4x1 mux full adder using 8x1 mux
VLSI-LEARNINGS
12.3K views·5 years ago
NAND gate using 2x1 mux inverter using NAND gate buffer using NAND gate
VLSI-LEARNINGS
5.1K views·5 years ago
sequence detector 0010 sequence detector 0011 overlapping mealy FSM
VLSI-LEARNINGS
16.2K views·5 years ago
sequence detector 1110 sequence detector 1111 overlapping mealy FSM
VLSI-LEARNINGS
15.8K views·5 years ago
sequence detector 0110 sequence detector 0111 overlapping mealy FSM
VLSI-LEARNINGS
15.3K views·5 years ago
Sequence detector 1100 sequence detector 1101 overlapping mealy FSM
VLSI-LEARNINGS
59.0K views·5 years ago
sequence detector 1000 sequence detector 1001 overlapping mealy FSM
VLSI-LEARNINGS
16.5K views·5 years ago
sequence detector 0100 sequence detector 0101 overlapping mealy FSM
VLSI-LEARNINGS
17.3K views·5 years ago



![[VLSI DIGITAL Verilog] Design full subtractor using Full adder full adder full subtactor](https://i.ytimg.com/vi/pB0U77vJi-8/hqdefault.jpg?sqp=-oaymwE2CNACELwBSFXyq4qpAygIARUAAIhCGAFwAcABBvABAfgB_g6AArgIigIMCAAQARgRIGsocjAP&rs=AOn4CLBXxCNXrD1Br2-aysy2Iglbty3GPw)

![[VLSI FIFO ] full and empty logic for FIFO verilog code for FIFO FIFO logic](https://i.ytimg.com/vi/XvbjSLOatSY/hqdefault.jpg?sqp=-oaymwEcCNACELwBSFXyq4qpAw4IARUAAIhCGAFwAcABBg==&rs=AOn4CLAxwciav_0i3XMOn8PlTISx1H3pnQ)



![[VLSI - VERILOG ] verilog code for counter increment by 2 test bench for counter](https://i.ytimg.com/vi/0eyDIXfPT3M/hqdefault.jpg?sqp=-oaymwEcCNACELwBSFXyq4qpAw4IARUAAIhCGAFwAcABBg==&rs=AOn4CLAlmOzQHt4g23Vi8igd6AHXEFu45A)



















