Shubha Hegde

Boolean Expression using CMOS Logic Y=(AB+CD+E)' Using Cadence virtuoso tool

Shubha Hegde

Layout-Common Source amplifier with PMOS current mirror load using Cadence virtuoso tool

Shubha Hegde

Simulation-Common Source amplifier with PMOS current mirror load using Cadence virtuoso tool

Shubha Hegde

Inverter Layout using Cadence virtuoso tool

Shubha Hegde

Inverter Simulation using Cadence virtuoso tool

Shubha Hegde

NOR Gate Layout using Cadence virtuoso tool.

Shubha Hegde

NOR Gate simulation using Cadence Virtuoso tool.

Shubha Hegde

CMOS NAND Gate Layout Using Cadence Virtuoso tool.

Shubha Hegde

NAND Gate Simulation using Cadence Virtuoso tool.

Shubha Hegde

4-bit adder verilog code verification using Cadence tool.

Shubha Hegde

CMOS Inverter layout Virtuoso tool

Shubha Hegde

CMOS INVERTER SIMULATION using cadence Virtuoso.

Shubha Hegde