This channel aims to help enthusiasts to learn 1. Verilog HDL 2. What is a simulation and what types of simulations are there? 3. What is meant by Synthesis ...
VerilogHDL
![Exp5 3bit multiplier using Gatelevel modelling[part2 - code]](https://i.ytimg.com/vi/vtcm1KD03gw/hqdefault.jpg?sqp=-oaymwE2CNACELwBSFXyq4qpAygIARUAAIhCGAFwAcABBvABAfgB_gmAAtAFigIMCAAQARhjIGMoYzAP&rs=AOn4CLBzSEAV3PZOc68kB-4YgHgwr_phjw)
![Exp5 3bit multiplier using Gatelevel modelling[part1-Theory]](https://i.ytimg.com/vi/hiE7vD6uk3Y/hqdefault.jpg?sqp=-oaymwE2CNACELwBSFXyq4qpAygIARUAAIhCGAFwAcABBvABAfgB_gmAAtAFigIMCAAQARhlIGUoZTAP&rs=AOn4CLDrR92GqFspPcsAQbAgfkzN_6v2Uw)
![Exp3 4bit rca using 1bit fa part2[Code]](https://i.ytimg.com/vi/CUU4bGOGFn4/hqdefault.jpg?sqp=-oaymwE2CNACELwBSFXyq4qpAygIARUAAIhCGAFwAcABBvABAfgB_gmAAtAFigIMCAAQARhZIGAoZTAP&rs=AOn4CLCfLFuNWW9orC-ZjLLTq6Ltxd0WBg)
![Exp3 4bit rca using 1bit fa part1[Theory]](https://i.ytimg.com/vi/m4Tq3HfWMOM/hqdefault.jpg?sqp=-oaymwE2CNACELwBSFXyq4qpAygIARUAAIhCGAFwAcABBvABAfgB_gmAAtAFigIMCAAQARhSIGEoZTAP&rs=AOn4CLAa2uFSnt-Qm324rnbU94Mj8McXDA)
![Exp2 mux4x1 using mux2x1 - Contd. [with how to display in console]](https://i.ytimg.com/vi/m5Kaqfk_ykI/hqdefault.jpg?sqp=-oaymwE2CNACELwBSFXyq4qpAygIARUAAIhCGAFwAcABBvABAfgB_gmAAtAFigIMCAAQARhbIGAoZTAP&rs=AOn4CLAsdVBkoyGSj0ZUW6unGvLzujkxew)