EG ELECTRONICS

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There are very less or almost no vedios for diploma students in Telugu , for understanding the topics clearly...this channel provide information for those st...

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Timing Controls and Conditional Statements

Procedural Assignments ,Blocking and Non Blocking Assignments

BEHAVIORAL MODELING PROCEDURES ALWAYS and INITIAL

PRIMITIVES AND RISE ,FALL ,TURN-OFF DELAY

HALF ADDER DESIGN WITH GATE LEVEL MODELING AND DATA FLOW MODELING

Compare Module and Instance

VLSI DESIGN FLOW

Importance of HDL & compare VHDL and VERILOG HDL

Instatiation and inference of a component

LEXICAL TOKENS

Verilog data types

Types of operaters used in verilog

@krishna_kanth #pd #sir c r r polytechnic

12 October 2025

12 October 2025

12 October 2025

12 October 2025

12 October 2025

12 October 2025

12 October 2025

12 October 2025

12 October 2025

LECTURE 3.1 DECIMAL TO BINARY CONVERSION

LECTURE 40 4 BIT RIGHT SHIFT REGISTER

LECTURE 39 4 bit left shift register

LECTURE 38 4 BIT SYNCHRONOUS COUNTER

అమరావతి మాస్టర్ ప్లాన్ డెమో

LECTURE 37 ASYNCHRONOUS 3 BIT UP DOWN COUNTER

LECTURE 36 Asynchronous Decade counter Mod 10 counter

LECTURE 35 4 BIT ASYNCHRONOUS COUNTER RIPPLE COUNTER