3:26[FPGA ]Verilog and Vivado - Day 10 system bus, point to point, pipeline, wafer, DMA, SerDesS2530 views·5 months ago
2:55[FPGA ]Verilog and Vivado - Day 9 example sending command to endpoint (pcie)S2531 views·5 months ago
3:58[FPGA ]Verilog and Vivado - Day 8 8b10b, failed to understand PCIe (will try again)S2530 views·5 months ago
5:17[FPGA ]Verilog and Vivado - Day 4 Vivado command line with VScode, implement delay, RAMS25148 views·6 months ago
2:12[FPGA] Verilog and Vivado - Day 1 Toggle LED, Run Behavior Simulation, Basic VerilogS2576 views·6 months ago