Shilpa Rudrawar

PART 1_Sequence Detector Basics and Mealy 101 Detector State Diagram Explained

Shilpa Rudrawar

Process Control Loop Explained

Shilpa Rudrawar

PART 2_Transistor Sizing in CMOS WL Ratio Explained with Example

Shilpa Rudrawar

PART 1_Transistor Sizing in CMOS Basics & Importance in VLSI Design

Shilpa Rudrawar

Stick Diagram in VLSI CMOS Layout Simplified

Shilpa Rudrawar

PART3_CMOS Combinational Logic Design for NOR & EXOR PMOS & NMOS Circuit Explained

Shilpa Rudrawar

Power Dissipation in CMOS Static, Dynamic & Leakage Power Explained

Shilpa Rudrawar

PART1_CMOS Inverter Working & VTC Curve Explained Voltage Transfer Characteristics

Shilpa Rudrawar

PART2_Technology Scaling in VLSI Field, Voltage & Lateral Scaling + MOSFET Effects

Shilpa Rudrawar

CMOS Transmission Gate Working, Design

Shilpa Rudrawar

PART1_Technology Scaling in VLSI Field, Voltage & Lateral Scaling

Shilpa Rudrawar

PART2_CMOS Combinational Logic Design for NOT, NOR & NAND PMOS & NMOS Circuit Explained

Shilpa Rudrawar

PART1_CMOS Combinational Logic Design for NOT & NAND PMOS & NMOS Circuit Implementation Explained

Shilpa Rudrawar

CMOS Fabrication Process Explained Step-by-Step IC Manufacturing VLSI & Semiconductor Basics

Shilpa Rudrawar

What is Body Effect in MOSFET MOSFET Concept Simplified

Shilpa Rudrawar

Pull-Up & Pull-Down Concept in PMOS & NMOS CMOS Logic Explained

Shilpa Rudrawar

What is Channel Length Modulation MOSFET Concept Simplified

Shilpa Rudrawar

MOSFET Fundamentals How They Work

Shilpa Rudrawar

Overlapping 1011 Sequence Detector on FPGA with Vivado Nexys Board Implementation

Shilpa Rudrawar

Step-by-Step GuideFPGA implementation of 1011 Mealy overlapping sequence Detector using Vivado Tool

Shilpa Rudrawar

Step-by-Step Guide Simulation of 1011 Mealy -overlapping sequence Detector using Vivado Tool

Shilpa Rudrawar

Verilog Code and Testbench for a 1011 Sequence Detector (Mealy - Overlapping)

Shilpa Rudrawar

1011 Sequence Detector (Mealy - Non-Overlapping Design)

Shilpa Rudrawar

1011 Sequence Detector (Mealy - Overlapping)

Shilpa Rudrawar

Part2-Basics of Finite State Machine (FSM) - Mealy and Moore

Shilpa Rudrawar

Part1-Basics of Finite State Machine (FSM) - Mealy and Moore

Shilpa Rudrawar

Step-by step Guide Simulation of 164 RAM using Xilinx Vivado tool

Shilpa Rudrawar

Verilog Testbech for 164 RAM

Shilpa Rudrawar

Verilog Code for 16x4 RAM module

Shilpa Rudrawar

Part4_Hardware Implementation of 4 bit Up- Down Counter

Shilpa Rudrawar