Bill Siever

Homework 7A washer demo

Bill Siever

Homework 7A delay() and spinner() demos

Bill Siever

CSE 2600 Homework 6B

Bill Siever

Washer State Machine Demo (Fall 2025)

Bill Siever

Pico RISC-V (32imc) on iCE40 UPduino

Bill Siever

Using the Dev Container for Custom HDL Projects

Bill Siever

RISC-V Assembly State Machine for Washer on Hardware

Bill Siever

Hardware Demo of the 7-segment cycle display (spinner)

Bill Siever

Using a Verilog Testbench to Debug ControlDatapath Errors

Bill Siever

Demonstration of the delay() function (1s, 2s, and 5s)

Bill Siever

RISC-V Assembly State Machine Demo

Bill Siever

Working with VSCode & Venus RISC-V Extension

Bill Siever

Homework 6A Demos

Bill Siever

ALU + Registers = Calculator

Bill Siever

ALU Demo

Bill Siever

Washer Statemachine Demo

Bill Siever

Statemachine Testbench Debugging

Bill Siever

Digital Logic Debugging

Bill Siever

JLS Basics

Bill Siever

Demo Dev Container for Digital Logic & Computer Design

Bill Siever

Understanding ProgramCPU and Verilog Behavior

Bill Siever

Debugging Verilog for `lui`

Bill Siever

CSE260M FL24 Homework 7 Counting State Machine via Code

Bill Siever

CSE260M FL24 Homework 7 Counting

Bill Siever

11.1 Data Structures & Algorithms Single-Source Shortest Path & Dijkstra's Algorithm

Bill Siever

12.5 Data Structures & Algorithms Kruskal's Algorithm for Minimal Spanning Trees

Bill Siever

12.4 Data Structures & Algorithms Greedy Algorithms, Prim's Algorithm, and Dijkstra's Algorithm

Bill Siever

12.3 Data Structures & Algorithms Justifying Prim's Algorithm is Optimal

Bill Siever

12.2 Data Structures & Algorithms Minimal Spanning Trees and Prim's Algorithm

Bill Siever

12.1 Data Structures & Algorithms More Graph Problems - Spanning Trees

Bill Siever