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CSA

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BUS

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Delay and Power Calculation on Cadence -Virtuoso

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Experiment 10B-ALL ZERO DETECTOR (Schematic, Symbol, Test Circuit) Design using Cadence

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Experiment11-PARITY GENERATOR-(Even and Odd) (Schematic, Symbol, Test Circuit) Design using Cadence

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Experiment 10A-ALL ONE DETECTOR (Schematic, Symbol, Test Circuit) Design using Cadence

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Experiment 9-MULTIPLIER -2X2 (Schematic, Symbol, Test Circuit) Design using Cadence

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Experiment 6-21 MUX (Schematic, Symbol, Test Circuit) Design using Cadence

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Experiment 7A-FULL ADDER (Schematic, Symbol, Test Circuit) Design using Cadence

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Experiment 7A-HALF ADDER (Schematic, Symbol, Test Circuit) Design using Cadence

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Experiment 8-1 BITCOMPARATOR (Schematic, Symbol, Test Circuit) Design using Cadence

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Experiment 5B-CMOS XNOR Gate (Schematic, Symbol, Test Circuit) design using Cadence

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Experiment 5A-CMOS XOR Gate (Schematic, Symbol, Test Circuit) design using Cadence

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Experiment-3-CMOS Inverter (Schematic, Symbol, Test Circuit, Layout) design using Cadence

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Experiment-2B--PMOS Pass Logic

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Experiment-1B-PMOS-VI Characteristics

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Experiment-2A--NMOS Pass logic

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Experiment-1A-NMOS-VI Characteristics

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Experiment-0--Cadence Tool Usage

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Tool usage guidance

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Keil u Vision-Tool installation

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STEPPER

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RELAY

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KEYPAD

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ASCII to BCD

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BCD to ASCII

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7 SEGMENT (Common Cathode) Interface to PIC18F452

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16X2 LCD interface to PIC18F452(MPLAB and Proteaus

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1 MPLAB INSTALLATION

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2 COMPILER INSTALLATION

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