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Merry Christmas and Happy New Year 2024

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Creating Multi-Boot Bitstream In Xilinx FPGA - Part One

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Xilinx HLS Project Demo - SHA256 Calculation

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Build A Soft Core CPU - Part Three - NIOS II in Intel FPGA

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Intel FPGA Development Workflow - Quartus Prime and MAX10 Demo

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Build A Soft Core CPU - Part Two - RISC-V in Xilinx FPGA

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Build A Soft Core CPU - Part One - MicroBlaze in Xilinx FPGA

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Rome Trip Opening

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调戏电话诈骗犯实录

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PetaLinux SPI Device Control LCD Panel - Project Demo

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Xilinx Zynq & PetaLinux Project Demo

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Adding DDR4 and video frame buffer on Xilinx KCU116 Eval Board

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Generate HDMI output on Xilinx KCU116 Eval Board

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Create and package IP in Xilinx Vivado block design

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Custom HW board defined in Xilinx Vivado and demo FPGA project creation

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Xilinx Vivado block design and Vitis demo

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Some moments of early age

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2006 PEO

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2017 Dominican Republic vacation

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Dominican opening

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Dream...Home... 两岸三地混搭，梦飞翔的地方 4K 2160P24

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