Anish Saha

12.4K subscribers

143 videos

Hi, let's learn, grow & explore while having fun! 😉 My hobbies are to travel around the world, Be productive and Obviously solving CIRCUITS!!! In my channel,...

Latest Videos

NVIDIA Hiring Off-Campus N.Ex.T 2026 Preparation Stategy & Resources Hardware Engineer

🔥RevisionX Notes For Analog & Digital VLSI Profile

🔥Complete VLSI Roadmap with Free & Paid Resources!

Struggling with VLSI Placements Anish Saha

Which is Better Digital or Analog VLSI Profile Career Scope & Opportunities Anish Saha

🔥RC Circuits Transient Response with Current Source Analog VLSI Placement Interview Questions

Best Way to Prepare for Campus Placements & Utilize Your Time Anish Saha

🔥100 Days Digital VLSI Roadmap with Free & Paid Resources!

Top Skills Every VLSI Engineer Should Learn in 2025 Anish Saha PrepFusion

Multilevel Cache, Cache Inclusion Policy Cache Memory Digital VLSI Anish Saha

Block Replacement & Types of Cache Miss Cache Memory Digital VLSI Anish Saha

🔥Digital VLSI Mastery Course Roadmap Complete Placement Guide Anish Saha PrepFusion

Hardware Implementation of Cache Mapping Cache Memory Digital VLSI Anish Saha

Assignment Solutions of Cache Mapping Cache Memory Digital VLSI Anish Saha

Set Associative Cache Mapping Cache Memory Digital VLSI Anish Saha

Questions in Direct Cache Mapping Cache Memory Digital VLSI Anish Saha

Direct Cache Mapping Cache Memory Digital VLSI Anish Saha

Cache Write Policies Assignment Solutions Cache Memory Digital VLSI Anish Saha

🔥Locality Of Reference, Avg Access Time Cache Memory Digital VLSI Anish Saha

5(C) Control & Structural Hazards in Instruction Pipelining Digital VLSI COA Anish Saha

5(B) Hazards in Instruction Pipelining Digital VLSI COA Anish Saha

5(A) Basics of Instruction Pipelining Digital VLSI COA Anish Saha

4(B) Microprogramming, RISC VS CISC Digital VLSI COA Anish Saha

4(A) Datapath & Control Unit (CU) Digital VLSI COA Anish Saha

Complete Verilog Course Launch Digital VLSI Anish Saha PrepFusion

9. Verilog Exercises Solutions Subtractor, Comparator, Counter, Synthesis #30daysofverilog

8(B) Verilog Operators, Data Flow Modeling, and Examples #30daysofverilog

8(A) Continuous Assignments assign Statement, Delays, and Concatenation #30daysofverilog

7. Verilog Assignment Solutions Gate-Level Design, Latches, Multiplexers, Delay #30daysofverilog

6. Verilog Gate Level Modeling Tutorial Gates, Adders, Delays, and Simulation #30daysofverilog