Anand Raj

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SUBSCRIBE 🔔& SUPPORT Welcome to my channel 🙏, Hi, My Name is Anand Raj. I love sharing my knowledge to help others. I create educational videos, vlogs, and m...

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Outing with team #qualcomm #hyderabad

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Village ➝ America

If I Can Do It, You Can Too! 🔥 0 to 70 Lakh Journey🔥😱

Lec.15 four bit parallel adder

Lec. 14 full adder using half adder

Lec.13 full adder

Lec.12 Testebench in details and system task and half adder

Lec. 11 Testbench basics

Lec.10 verilog structure

Lec.9 blocking and nonblocking

Lec.8 Assignment statement

Lec.7 operators

Lec. 6 scalar vector array

Lec. 5 data types

Lec.4 syntax and rule

Lec.3 Different style of modeling

Lec.2 What is Verilog and its history

Lec. 16.4 Effect of OCV on setup and hold time Static Timing Analysis RTL to GDSII flow

Lec. 16.3 how to calculate setup and hold slack Static Timing Analysis RTL to GDSII flow

Lec. 16.2 How to calculate maximum frequency Static Timing Analysis RTL to GDSII flow

Lec. 16.1 How to check setup and Hold Violation Static Timing Analysis RTL to GDSII flow

Lec. 18 Physical Verification and signoff on tool RTL to GDSII flow

Eight among twenty chips fabricated by IIT HYDERABAD🎉🔥 14th convocation #iithyderabad

Lec. 17 Physical Verification DRC LVS ERC RTL to GDSII flow

Lec. 16 Static Timing Analysis RTL to GDSII flow

Lec 15.1 Parasitic Extraction in innovus RTL TO GDSII Flow

Lec. 15 Routing RTL to GDSII flow

Lec 14.1 Clock Tree Synthesis on tool CTS RTL to GDSII Flow

Lec. 14 Clock Tree Synthesis CTS RTL to GDSII flow