SiliconTech - Sanjucta Choudhury

Hardware Modeling of Blocking and Non Blocking Assignments

SiliconTech - Sanjucta Choudhury

𝐄𝐯𝐞𝐧𝐭 𝐐𝐮𝐞𝐮𝐞𝐬 𝐢𝐧 𝐕𝐞𝐫𝐢𝐥𝐨𝐠 (𝐀𝐜𝐭𝐢𝐯𝐞, 𝐈𝐧𝐚𝐜𝐭𝐢𝐯𝐞, 𝐍𝐁𝐀, 𝐏𝐨𝐬𝐭𝐩𝐨𝐧𝐞𝐝) 𝐰𝐢𝐭𝐡 𝐒𝐦𝐚𝐥𝐥 𝐄𝐱𝐚𝐦𝐩𝐥𝐞𝐬

SiliconTech - Sanjucta Choudhury

STA Numerical- PART2

SiliconTech - Sanjucta Choudhury

STA Setup and Hold Time Requirement with Solved Numerical (PART1)

SiliconTech - Sanjucta Choudhury

𝐈𝐧𝐭𝐞𝐫𝐯𝐢𝐞𝐰 𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧 -Mod 5 counter or f5 circuit with 50% duty cycle

SiliconTech - Sanjucta Choudhury

Beauty of FSM & 101 sequence detector FSM both overlap and non overlapping cases (Mealy Moore)

SiliconTech - Sanjucta Choudhury

Asynchronous FIFO- Architecture and pseudo code explanation with FIFO depth numerical

SiliconTech - Sanjucta Choudhury

Neural Network in System Verilog - Select Max layer part7

SiliconTech - Sanjucta Choudhury

Neural_Network in System Verilog - Neuron Module part4

SiliconTech - Sanjucta Choudhury

Neural Networks in System Verilog- Files Hierarchy (PART 2)

SiliconTech - Sanjucta Choudhury

Neural Network in System Verilog - Simulation Output-part 8

SiliconTech - Sanjucta Choudhury

Neural Network in System Verilog - Relu and Vanishing Gradients problem in Sigmoid-part6

SiliconTech - Sanjucta Choudhury

Neural Network in System Verilog- Dense_layer1 &2- part 5

SiliconTech - Sanjucta Choudhury

Neural Network in System Verilog - part 3 - Pooling layer

SiliconTech - Sanjucta Choudhury

Neural Network in System Verilog -Introduction Part1

SiliconTech - Sanjucta Choudhury