10:01V0. Intro Video of Verilog HDL Course Real-Life Applications and VLSI Career InsightsPrasanna_VLSI_KT379 views·1 year ago
40:34V23. User-Defined Primitives and Verilog Tasks & Functions Practical ExamplesPrasanna_VLSI_KT196 views·1 year ago
52:15V22. CMOS Design in Verilog HDL Inverter, Gates, MUX, Latch, and Delay ModelsPrasanna_VLSI_KT133 views·1 year ago
30:04V21. Exploring Switch-Level Modeling in Verilog HDL MOS and Bi-Directional SwitchesPrasanna_VLSI_KT368 views·1 year ago
38:40V20. Live Verilog Coding Behavioral Modeling with Non-Synthesizable Delays and For Loop AnalysisPrasanna_VLSI_KT20 views·1 year ago
39:20V19. Advanced Verilog HDL Loop Examples, Block Structures, and Practical DesignsPrasanna_VLSI_KT28 views·1 year ago
37:50V18. Verilog HDL Essentials Conditional Statements, Multiway Branching, and LoopsPrasanna_VLSI_KT98 views·1 year ago
24:53V17. Live Verilog Coding Clock Divider Techniques and FPGA Delay ImplementationPrasanna_VLSI_KT324 views·1 year ago
31:46V16. Mastering Event-Based Timing Control in Verilog HDL Live Coding Blocking vs Non-Blocking ex.Prasanna_VLSI_KT94 views·1 year ago
28:06V13. Live Coding Verilog Multiplexer with Assign Statements, exploring the implications of scalingPrasanna_VLSI_KT13 views·1 year ago
33:32V12. Live Coding with Verilog Data Flow Operators and FPGA Resource Utilization InsightsPrasanna_VLSI_KT15 views·1 year ago
45:07V9. Live Verilog coding 4-Bit Ripple Carry Adder Synthesis and FPGA Signal Flow AnalysisPrasanna_VLSI_KT85 views·1 year ago
43:01V15. Advanced Behavioral Modeling in Verilog HDL Blocking vs Non-Blocking AssignmentsPrasanna_VLSI_KT35 views·1 year ago
41:31V14. Behavioral Modeling in Verilog HDL Timing Control and Procedural AssignmentsPrasanna_VLSI_KT44 views·1 year ago
50:12V11. Digital Design with Verilog HDL Exploring Data Flow Modeling and Assign StatementsPrasanna_VLSI_KT12 views·1 year ago
42:12V8. Live Verilog Coding Gate-Level Modeling with Test Benches and FPGA ComparisonsPrasanna_VLSI_KT15 views·1 year ago
1:06:31V7. Digital Design with Verilog HDL Gate-Level Modeling and Logic Gate PrimitivesPrasanna_VLSI_KT49 views·1 year ago
32:48V6. Live Verilog Coding Ripple Carry Adder Simulation and FPGA Implementation on Zed BoardPrasanna_VLSI_KT71 views·1 year ago
46:46V5. Live Verilog Coding in Vivado Basics, Data Types, and SR Latch SimulationPrasanna_VLSI_KT86 views·1 year ago
45:33V4. Hands-On Digital Design with Verilog HDL Exploring Modules, Ports, and More Part 2Prasanna_VLSI_KT64 views·1 year ago
55:23V3. Hands-On Digital Design with Verilog HDL Exploring Modules, Ports, and MorePrasanna_VLSI_KT86 views·1 year ago
9:35V2. Hands-On Digital Circuit Design From Logic Gates to Real-World Applications - Part 1Prasanna_VLSI_KT102 views·1 year ago
52:45V1. Hands-On Digital Circuit Design From Logic Gates to Real-World Applications - Part 1Prasanna_VLSI_KT127 views·1 year ago