[23] PIC12F683 part 3: Risk mitigation, floorplan analysis

In part 3 of the PIC12F683 series, I discuss some of the engineering and procedural controls used to ensure safe sample preparation, then analyze the device floorplan to identify blocks of interest for further circuit analysis. Full res photos: http://siliconprawn.org/map/microchip/pic12f683/ Part 2: https://www.youtube.com/watch?v=Ad2Th6oio6c&list=PLBNA3N3RCc8oRO_tnl_lnhJU61hRJ6qbU Part 4: https://www.youtube.com/watch?v=iRv2Msufy3w&list=PLBNA3N3RCc8oRO_tnl_lnhJU61hRJ6qbU 00:00 - Introduction 00:30 - Risk mitigation during decapsulation process 06:16 - Top metal floorplan overview 06:52 - Substrate floorplan overview 07:10 - Flash memory 08:05 - SRAM 08:47 - EEPROM 09:09 - northwest analog blocks 09:53 - CPU core 11:10 - configuration register ("fuses") 14:03 - northeast analog blocks 14:56 - Bond pads, pad ring, I/O cells 16:13 - MCLR / Vpp I/O circuit 17:56 - device size, cell library specs, concluding remarks