In this demo, we walk through building a Vector Quantizer / Dequantizer (VQ/DQ) chiplet IP based on the open-source Lyra Codec, using the Vyges platform.
You’ll see how Vyges metadata conventions drive:
- IP scaffolding (architecture + design specs)
- SystemVerilog and Cocotb testbenches with VCD waveform generation
- Chiplet-ready integration with UCIe interfaces
- CI automation and reporting scripts
- Catalog-ready publishing for reuse
This workflow demonstrates how Vyges allows engineers to focus on algorithm development while automating boilerplate, verification, and packaging — essentially, building silicon like software.
Google’s Lyra codec - https://research.google/blog/soundstream-an-end-to-end-neural-audio-codec/
Reference C++ implementation - https://github.com/google/lyra
Learn more at https://vyges.com
."* #Vyges #LyraCodec #ChipletIP #SystemVerilog #Cocotb #ASICDesign #MetadataDrivenIP #DSP #AudioIP
