In this video, I explain CMOS Delay in VLSI design based on Chapter 4 of the book
"CMOS VLSI Design: A Circuits and Systems Perspective" by Neil H. E. Weste & David Money Harris.
🔹 Topics Covered:
1. Different types of delay in CMOS circuits
2. RC Delay Model
3. 3-input NAND gate design with NMOS & PMOS
+ Equivalent circuits for falling & rising output transitions
4. Transient Response
5. Elmore Delay
6. Layout Dependence of Capacitance
7. Linear Delay Model
8. Logical Effort of Path
9. Minimum Delay Path Calculation (Problem Solving)
10. Choosing the Optimal Number of Stages
This lecture is useful for students, researchers, and professionals learning **VLSI, CMOS circuits, and digital design optimization**.
📘 Reference: CMOS VLSI Design: A Circuits and Systems Perspective by Weste & Harris
#CMOS #VLSI #DelayModel #LogicalEffort #Electronics #Engineering
