Heterogeneous IC Packaging for Optimizing Performance and Cost

Leading integrated circuit (IC) foundries are already shipping 7 nm and 5 nm process node wafers and will soon be shipping 3 nm. At the same time, wafer costs continue to soar as high transistor densities require ever more expensive processing to fabricate them. Even if defect densities can remain relatively flat as new nodes emerge, the cost per unit area of silicon is increasing nonlinearly. These economics have placed a new packaging technology squarely into the discussions for future product architectures. Heterogeneous Packaging has been the packaging industry’s answer. It enables a design approach that has been the industry’s holy grail for a long time but has only recently become practical. Portions of what would have been a single-die, system on chip (SoC) are being carved out of the homogenous designs and created in smaller, independent silicon die. The first trend has been to remove the I/O blocks that communicate to the memory and also long reach serializer/deserializer (SerDes) circuitry as well. This design methodology creates an electrical, functional and physical building block repository whereby IC functional blocks can be qualified and reused over and over. Spreading the original investments over a larger number of end devices in this manner was nearly unthinkable just a few years ago. The industry initiated this most recent evolution with 2.5D Through Silicon Via (TSV) products, which allow very high-density DRAM (High Bandwidth Memory or HBM) to be implemented alongside the application-specific integrated circuit (ASIC) in the same IC package. Now, functional blocks are being removed from SoCs. Examples include central processing units (CPUs) as stand-alone silicon chiplets, as productized in AMD’s recent server and Accelerated Processing Unit (APU) offerings, the EPYC™ and Ryzen™ series. To address these offerings, Amkor has developed several key packaging technologies for a few or many die into a high-performance collection of discrete die including logic, memory and more. These developments include high-density multi-die offerings utilizing conventional package substrates and Advanced SiP and Flip Chip BGAs (FCBGAs) as well as very fine-line constructions such as 2.5D TSV and High-Density Fan-Out (HDFO) offerings. New chiplet integrations using advanced HDFO (S-SWIFT®) are now being qualified that permit fine line routing down to 2 µm line and 2 µm space with 4-layer construction. This module fabrication technology has been developed over the last 3 years and upgraded to realistically permit the integration of chiplets and HBM designs. The future of these packaging technologies is bright. In just the last year, new product designs in this packaging class have increased 4-fold. The silicon architectural flexibility, IP reuse, time-to-market and lower overall cost continue to drive this innovation in our industry as Amkor continues to deliver advances in Heterogeneous IC Packaging. S-SWIFT® is a registered trademark of Amkor Technology, Inc. All trademarks are the property of their respective owners. Presented by Mike Kelly, VP, Advanced Package & Technology Integration at Amkor Technology Originally presented at IMAPS Device Packaging Conference, April 12-15, 2021. Visit Devicepackaging.org for details about next year’s Conference.