Interface Protocol Part 3D: QSPI Flash Controller IP Design

In this Part 3D of the Interface Protocol series, we dive deep into QSPI Flash Controller IP design, covering detail simulation of read related commands. #QSPI #FlashMemory #FPGA #RTLDesign #EmbeddedSystems #Verilog #VHDL #SPIProtocol #OpenSource #electronics rtl code + simulation on vcs so please stay with me. In this video following read related commands covered for simulation CMD_READ_DATA 8'h03 CMD_FAST_READ 8'h0B CMD_FAST_READ_DUAL_IO 8'hBB CMD_FAST_READ_DUAL 8'h3B CMD_FAST_READ_QUAD_IO 8'hEB CMD_FAST_READ_QUAD 8'h6B CMD_W4READ 8'hE7 data_at_100000.hex @ 100000h 01 02 03 1f 05 06 07 08 02 00 00 10 00 80 80 80