Interface Protocol Part 3E: QSPI Flash Controller IP Design

In this Part 3E of the Interface Protocol series, we dive deep into QSPI Flash Controller IP design, covering detail simulation of Register access and device related commands. #QSPI #FlashMemory #FPGA #RTLDesign #EmbeddedSystems #Verilog #VHDL #SPIProtocol #OpenSource #electronics rtl code + simulation on vcs In this video following Register access and device related commands covered for simulation CMD_JEDEC_ID (9Fh) CMD_RES (ABh) CMD_READ_SR1 (05h) CMD_WRITE_ENABLE (06h) → CMD_WPSEL (68h) CMD_RDDPB (E0h) CMD_WRITE_ENABLE (06h) → CMD_WRDPB (E1h) CMD_RDDPB (E0h) CMD_WRITE_ENABLE (06h) → CMD_GLOBAL_BLOCK_UNLOCK (98h) Final CMD_RDDPB (E0h) data_at_100000.hex @ 100000h 01 02 03 1f 05 06 07 08 02 00 00 10 00 80 80 80