Interfacing DDR with Programmable Logic on the Versal NoC

This introduction to the AMD Versal NoC will demonstrate how to quickly interface your PS and PL to DDR through the recently introduced ACAP NoC Architecture. The introduction will be followed by a live demo. AMD Xilinx Authorized Training Provider and Premier Partner, BLT (Bottom Line Technologies),presents this webinar. For a complete list of upcoming live events and on-demand webinars from BLT, visit bltinc.com.