Approximately Timed (AT) Modeling can be used for Performance Modeling of Designs. AT is an abstraction level where timing points are introduced and are represented by phases. The TLM 2.0 standard defines three schemes in general. These are single phase, two phase and four phase. These schemes can be extended by definition of custom phases.
T&VS has been involved in performance modeling of System-on-Chip (SoC) blocks. Models are being developed for blocks such as LPDDR4 Memory Controller, AXI4 bus etc. Custom phases have been introduced where applicable and the TLM 2.0 Generic Payload is used as much as possible.
