// Code your design here
module and1 (y, a, b);
input a;
input b;
output y;
// assign y = a&b;
xor (y, a, b);
endmodule
//testbench
// Code your testbench here
// or browse Examples
`timescale 1ns / 1ps
module tb();
reg a;
reg b;
wire y;
and1 f(y, a, b);
initial begin
$dumpfile("dump.vcd"); $dumpvars;
a = 0; b=0;
#10 a = 0; b=1;
#10 a = 1; b=0;
#10 a = 1; b=1;
#10 $finish ;
end
initial begin
$monitor($time, " a=%b, b=%b, y=%b,", a, b, y);
end
endmodule
