DARClab

Bespoke Behavioral Processor

DARClab

Qt-based open source High-Level Synthesis Design Space Exploration framework

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MWSCAS 2019 Social Event

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HLS DSE fyp (Yujian Xiao -2016)

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AS2CBench video

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Innovative Technology Series (ITS) Training Workshop - High-Level Synthesis

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SystemC concurrency modelling

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Makefile

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Encrypt Behavioral IPs

DARClab

FPGA based Ping Pong game

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Speech visualization for Xilinx ML402 board

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FPGA based HW Acceleration

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Hardware-Based Face Detection

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FPGA based face detection

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High-Level Synthesis Design Space Explorer

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Web based High-Level Synthesis

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C based formal verification

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High-Level Synthesis Design Space Exploration (DSE)

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adder 4bit schematic

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High-Level Synthesis (HLS) theory

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SystemC Part 5 Verification

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Linux SW development

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Control Linux from Windows using Cygwin

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Xilinx ISE 1-bit full adder

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SystemC part4 Logic Synthesis

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SystemC part3 High-Level Synthesis

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SystemC part2 -including S2CBench -

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SystemC part1

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