FPGA - Getting Started 2a - Lab Timer #0128

In part 2 of Getting started with FPGAs Pete builds a lab timer so that he can start exploring clocking, counting, multiplexing and much more. In this video he gets as far as a fully working working 10mS timer, but he wants to improve it further and so is going to release part B in which he explores how to apply some digital desing best practices to make it more precise, and to make the modules high quality and reusable in very high-speed designs. Links to GitHub will be added once I publish part B Some of the resources I have used 🔸AMD UltraFast Degin Methodology https://docs.amd.com/r/en-US/ug949-vivado-design-methodology 🔸7 Series FPGAs Clocking Resources https://docs.amd.com/v/u/en-US/ug472_7Series_Clocking 🔸https://www.chipverify.com/systemverilog/systemverilog-datatypes 🔸Book SystemVerilog for design second edition - Expensive but you will find a PDF online if you can't afford it - also available online of you have membership of certain professional and academic institutions 🔸SystemVerilog Specification https://rfsoc.mit.edu/6S965/_static/F24/documentation/1800-2017.pdf 🔸Nice and concise https://sutherland-hdl.com/papers/2013-SNUG-SV_Synthesizable-SystemVerilog_paper.pdf To help me keep the channel going please consider the following links: 🔸Topcashback https://www.topcashback.co.uk/ref/pshersby . As well as all the usual shops this site offers cashback from Farnell, RS Online, Rapid, ebay and plenty more too. Please make sure you sign up using the link above so that both you and I get a sign-up bonus! At time of writing that is £10 for you once you earn £10 cashback, there is a no fees option and you can take as long as you like to accure the £10 cashback. 🔸Octopus Energy is offering £50 for new customers if you sign up with this link http://share.octopus.energy/sunny-ape-959 🔸Donations always welcome! https://www.paypal.com/paypalme/PeterShersby As always please help by subscribing and liking videos. 🔸 https://www.youtube.com/channel/UCDGlaK7fh5ZY6nFLznaHgZw?sub_confirmation=1 00:00 - Start 00:02 - Intro 00:23 - Project outline 01:31 - Seven Segment Encoder 02:59 - Parameter v.s. port 03:39 - New Data Types 04:20 - Always_comb, Always_ff and always_latch 06:25 - Test Bech - ChatGBT 09:31 - Simple Clock Divider 13:52 - Blocking v.s. non-blocking 15:09 - Clarifying always_ff 16:14 - Multiplexed Display 23:40 - Top Level Module First Draft 24:50 - Critical clocking and Power Warnings 26:16 - Te 100Hz BCD Counter Timer 28:27 - Async Enable makes inaccurate 29:31 - Complete Top Level Code 31:27 - Async Reset 33:06 - Generate Blocks 34:19 - Generate - Genvar 36:03 - Making SystemVerilog Ports Compatible with VErilog