FPGA Static Timing analysis #0130

Is it fast enough, does the data line up, why does it glitch? Pete takes a moment to explain Static Timing Analysis and how to answer all these questions and more. Attributions 🔸 Standard deviation graph By Melikamp - Own work, CC BY-SA 4.0, https://commons.wikimedia.org/w/index.php?curid=65001875 To help me keep the channel going please think about using the following links: 🔸Topcashback https://www.topcashback.co.uk/ref/pshersby . As well as all the usual shops this site offers cashback from Farnell, RS Online, Rapid, ebay and plenty more too. Please make sure you sign up using the link above so that both you and I get a sign-up bonus! At time of writing that is £10 for you once you earn £10 cashback, there is a no fees option and you can take as long as you like to accure the £10 cashback. 🔸Octopus Energy is offering £50 for new customers if you sign up with this link http://share.octopus.energy/sunny-ape-959 🔸Donations always welcome! https://www.paypal.com/paypalme/PeterShersby As always please help by subscribing and liking videos. 🔸 https://www.youtube.com/channel/UCDGlaK7fh5ZY6nFLznaHgZw?sub_confirmation=1 00:00:00 - Start 00:00:02 - Intro 00:01:05 - Foundations 00:01:32 - Combinatorial Delays 00:06:21 - Register or Flip-flop Setup, hold, pulse width 00:08:03 - Combinatorial + Register in Use 00:16:08 - Simulation vs. STA 00:18:07 - Uncertaintry and Skew 00:18:39 - Skew 00:23:26 - Skew Source Synchronous Input 00:25:47 - Internal Skew 00:30:22 - Routing is slow = delay + skew 00:32:40 - Slew 00:38:40 - Jitter 00:43:10 - PVT 00:48:28 - Timing in Action - Vivado 00:57:36 - A Better Clock