Learn about the RISC-V instruction set architecture by building hardware. In this video, I use Logisim to build a 32-bit program counter that will eventually be incorporated into an RV32I CPU that can be synthesized on to an FPGA.
There are a number of resources that I recommend you study as you go on this journey with me:
RISC-V Green Sheet: https://inst.eecs.berkeley.edu/~cs61c/su18/img/riscvcard.pdf
Design of the RISC-V Instruction Set Architecture: https://digitalassets.lib.berkeley.edu/techreports/ucb/text/EECS-2016-1.pdf
Great Ideas in Computer Architecture (week 2 and 4): https://inst.eecs.berkeley.edu/~cs61c/su18/
Other helpful resources:
Online RISC-V assembler: https://riscvasm.lucasteske.dev
Logisim Evolution: https://github.com/logisim-evolution/logisim-evolution/releases
