Wasing machine controller using Basys3 FPGA board

This video presents the design and implementation of FPGA-based Washing Machine Controller using Verilog HDL on the Basys-3 FPGA development board. The controller automates the washing process through a finite state machine (FSM) architecture consisting of multiple operational stages including Soak, Wash, Rinse, and Spin cycles. The system integrates real-time countdown display using multiplexed 7-segment displays, user-selectable washing modes, lid safety detection, and timer-based control logic. The design is synthesized using Xilinx Vivado Design Suite and implemented on Artix-7 FPGA hardware. Compared to traditional mechanical or microcontroller-based washing machine controllers, the FPGA implementation offers improved reliability, parallel execution, low latency, and precise timing control. Video is prepared by Sahil Ariwala, Shristi Shah, Vansh Patel, Unnati Vamja